1. Field of the Invention
The present invention relates generally to a semiconductor device, and more particularly, to a transistor for preventing and reducing short channel effect and a method for manufacturing the same.
2. Description of Related Technology
As a design rule is rapidly reduced with an increase in integration of semiconductor devices, a channel length of a transistor has also been shortened. As the channel length of the transistor is shortened, problems caused by short channel effect degrade operation properties of the device. The short channel effect is generated as a width of a depletion region, generated between a substrate and a source, or between the substrate and a drain, is increased when a junction is formed on the substrate. When the channel length is shortened, intensity of an electric field is increased in the vicinity of a drain region. When the intensity of the electric field is increased, leakage current is generated in a capacitor unit in a cell region, and this leakage current deteriorates refresh properties of the device. Also, when the intensity of the electric field is increased, hot carriers and punch-through are generated and the operation properties and stability of the device are thus lowered.
Accordingly, to prevent or reduce a short channel effect, methods capable of ensuring an effective channel length without an increase in the design rule are desirable. In a method of ensuring an effective channel length, a recess gate in which a recess trench is formed within a substrate or a step gate in which a gate electrode is formed in a stepped form are typically employed to lengthen the channel. By employing gates with increased channel length through structural modification, it is possible to increase margins for the prevention of hot carrier generation and punch-through.
However, it is difficult to achieve a device operating at high speed because drain saturation current (IDsat) is noticeably reduced with the increase in the channel length. For example, in a peripheral region of a Dynamic Random Access Memory (DRAM) device, the leakage current is increased due to Drain Induced Barrier Lowering (DIBL) phenomenon when a drain-source voltage (Vds) is increased to increase the saturation current. The DIBL phenomenon means that a potential energy barrier is lowered by interaction of the source and the drain as the channel length is reduced. The potential energy barrier for electrons in the channel is lowered. The aforementioned problems caused by short channel effect and the DIBL phenomenon depend on the width of the depletion region and the electric field generated upon formation of a junction region using an ion implantation process. Accordingly, a method capable of controlling the width of the depletion region and the intensity of the electric field and preventing the degradation of device properties is desirable.